1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide the gate. Thereafter, the gate provides an implant mask during the implantation of source and drain regions, and the implanted dopants are driven-in and activated using a high-temperature anneal that would otherwise melt the aluminum.
An important parameter in IGFETs is the threshold voltage (V.sub.T), which is the minimum gate voltage required to induce the channel. In general, the positive gate voltage of an N-channel device must be larger than some threshold voltage before a conducting channel is induced, and the negative gate voltage of a P-channel device must be more negative than some threshold voltage to induce the required positive charge (mobile holes) in the channel. There are, however, exceptions to this general rule. For example, depletion-mode devices already have a channel with zero gate voltage, and therefore are normally on. With N-channel depletion-mode devices a negative gate voltage is required to turn the devices off, and with P-channel depletion-mode devices a positive gate voltage is required to turn the devices off
If the source and body of an IGFET are tied to ground, the threshold voltage can be calculated as follows: EQU V.sub.T =.phi..sub.ms -2.phi..sub.f -Q.sub.tot /C.sub.ox -Q.sub.BO /C.sub.ox -.DELTA.V.sub.T ( 1)
where .phi..sub.ms is the work-function difference between the gate material and the bulk silicon in the channel, .phi..sub.f is the equilibrium electrostatic potential in a semiconductor, Q.sub.tot is the total positive oxide charge per unit area at the interface between the oxide and the bulk silicon, C.sub.ox is the gate oxide capacitance per unit area, Q.sub.BO is the charge stored per unit area in the depletion region, and .DELTA.V.sub.T is a threshold lowering term associated with short-channel effects. Expressions have been established for these various quantities in terms of doping concentrations, physical constants, device structure dimensions, and temperature. For example, the work-function difference .phi..sub.ms varies as a function of the doping concentration in a polysilicon gate. Therefore, the threshold voltage depends on the doping concentration in the polysilicon gate.
Photolithography is frequently used to create patterns in photoresist that define where the polysilicon layer is etched to form the polysilicon gate. The photoresist has the primary functions of replicating an irradiated image pattern and protecting the underlying polysilicon when etching occurs.
Typically positive photoresist is used, the irradiated portions are rendered soluble to a subsequent developer, and the non-irradiated portions remain insoluble to the developer and provide the etch mask. Unfortunately, increasing the photoresist thickness generally decreases the accuracy in which the photoresist replicates the image pattern. Since, however, the photoresist is eroded by the etch, the photoresist must be thick enough to avoid being removed by the etch. The photoresist is often on the order of 4 times as thick as the underlying polysilicon to assure that the etch does not remove the photoresist.
For submicron geometries, the gate thickness is usually on the order of 2000 to 2500 angstroms so that during ion implantation of the source and drain, the gate provides an implant mask for the underlying channel region yet also receives sufficient doping to attain the desired threshold voltage. Unfortunately, the photoresist that defines the gate may have a thickness on the order of 8000 to 10,000 angstroms, which may be too large to accurately replicate the image pattern. Variations in photoresist linewidth can lead to variations in gate length ( the critical dimension), which in turn can lead to variations in channel length and ultimately device performance.
Accordingly, a need exists for an improved method of making an IGFET that provides an adequately doped polysilicon gate and reduces unwanted variations in gate length and device performance.